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36 v,1 a, synchronous, step - down dc - to - d c regulator data sheet ADP2441 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is ass umed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or p atent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com f ax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features wide input voltage range of 4.5 v to 36 v low m inimum on time of 50 ns maximum load current of 1 a high efficiency of up to 9 4 % adjustable output down to 0.6 v 1 % output voltage accuracy adjustable switching frequency of 3 00 k hz to 1 mhz pulse skip mode at light load for power saving precision enable input pin open - drain p ower good external soft star t with tracking overcurrent - limit protection shutdown current of less than 15 a uvlo and thermal shutdown 12- lead, 3 mm 3 mm lfcsp package appli c ations point of l oad applications distributed power systems industrial control supplies standard rail conversion to 24 v / 12 v/5 v/3.3 v general description the ADP2441 is a constant frequency, current mode c ontrol, synchronous , step - down dc - to - dc regulator that is capable of driving loads up to 1 a with excellent line and load regulation characteristics. the ADP2441 operates with a wide input voltage range of 4.5 v to 36 v, which makes it ideal for regulating power from a wide variety of sou rces. in addition, the ADP2441 has very low minimum on time (50 ns) and is, therefore, suitable for applications requiring a very high step - down ratio. the output voltage can be adjust ed from 0.6 v to 0. 9 v v in . high efficiency is obtained with integrated low resistance n - channe l mosfets for both hig h - side and low - side devices. the switching frequency is adjustable from 300 khz t o 1 mhz with an external resistor. the ADP2441 also has an accurate power - good (pgood) open - drain output signal. at light load conditions , the regulator operates in pulse skip mode by skipping pulses and redu cing switching losses to improve energy efficiency. in addition, at medium to heavy load conditions, th e regulator operates in fixed frequency pulse - width mo dulat ion (pwm) mode to red uce electromagnetic interference ( emi ) . typical circuit conf iguration fb comp en pgood freq ss/trk pgnd vin sw bst agnd vcc ADP2441 c4 c3 c bst c in c out r top r freq r comp c comp r bottom v out 10581-001 v out v in figure 1. 0 20 40 60 80 100 10 30 50 70 90 0.02 0.2 1 efficienc y (%) load (a) v out = 3.3v 10581-002 v out = 5v v out = 12v v in = 24v f sw = 300khz figure 2. efficiency vs. load current , v i n = 24 v the ADP2441 us es hiccup mode to protect the ic from short circuits or from overcurrent conditi ons on the output . the external programmable soft start limit s inrush current during startup for a wide variety of load capacitances . o ther key features include tracking, input under voltage lockout (uvlo), thermal shutdown (tsd), and precision enable (en), which can also be used as a logic level shutdown input . the ADP2441 is available in a 3 mm 3 mm, 12 - lead lfcsp package and is rated for a junction temperature range of ? 40 c to + 125 c . www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical circuit configuration ......................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 internal block diagram ................................................................. 14 theory of operation ...................................................................... 15 control architecure ................................................................... 15 adjustable frequency ................................................................. 16 power good ................................................................................. 16 soft start ...................................................................................... 16 trac king ....................................................................................... 16 undervoltage lockout (uvlo) ............................................... 17 precision enable/shutdown ...................................................... 17 current - limit and short - circuit protection .......................... 17 thermal shutdown ..................................................................... 17 applications information .............................................................. 18 selecting the output voltage .................................................... 18 setting the switching frequency .............................................. 18 soft start ...................................................................................... 19 external components selection ............................................... 19 boost capacitor .......................................................................... 21 vcc capacitor ............................................................................ 21 loop compensation .................................................................. 21 large signal analysis of the loop compensation ................. 21 d esign example .............................................................................. 23 configuration and components selection ............................. 23 system configuration ................................................................ 24 typical application circuits ......................................................... 25 design example .......................................................................... 25 other typical circuit configurations ..................................... 26 power dissipation and thermal considerations ....................... 29 power dissipation ....................................................................... 29 thermal consid erations ............................................................ 29 evaluation board thermal performance .................................... 30 circuit board layout recommendations ................................... 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 6 / 12 rev ision 0: initial version www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 3 of 32 specifications v in = 4.5 v to 36 v , t j = ? 40c to +125c, unless otherwise noted. table 1 . parameter symbol test conditions /comments min typ max unit power supply input voltage range v in 4.5 36 v supply current i vin v en = 1.5 v not switching 1.7 2 .2 ma shut down current i shdn v en = agnd 10 1 5 a uvlo threshold v uvlo v in falling 3.8 4 4.2 v hysteresis 200 mv internal regulator regulator output voltage v cc v in = 5 v to 36 v 5 5.5 v output output voltage range v out 0.6 0.9 v in v maximum output current i out 1 a feedback regulation voltage v fb t j = ?40c to +85c 0.594 0.6 0.606 v t j = ?40c to +125c 0.591 0.6 0.609 v line regulation 0.0 0 5 %/v load regulation 0.0 5 %/a error amplifier feedback bias current i fb_bias v fb = 0.6 v 50 200 na transconductance g m i comp = 20 a 2 00 250 300 a/v open - loop voltage gain 1 a vol 65 db mosfets high - side switch on resistance 2 r ds_h (on) bst ? sw = 5 v 170 270 m? low - side switch on resistance 2 r ds_l (on) v cc = 5 v 120 180 m? leak age current i lkg v en = agnd 1 25 a minimum on time 3 t on_min all switching frequencies 5 0 65 ns minimum off time 4 t off_min 165 175 ns current sense current sense amplifier gain g cs 1.6 2 2.4 a/v hiccup time f sw = 300 khz to1 mhz 6 ms nu mber of cumu lative current - limit cycles to go into hiccup mode 8 events peak current limit i cl 1.4 1.6 1.8 a frequency switching frequency range f sw 300 1000 khz frequency set accuracy freq pin = 308 k ? 270 300 330 khz freq pin = 92.5 k ? 900 1000 110 0 khz soft start soft start current i ss v ss = 0 v 0.9 1 1.2 a precision enable input threshold v en( rising ) 1.15 1.20 1.25 v hysteresis v en(hyst) 100 mv leakage current i ien_leak v in = v en 0.1 1 a thermal shutdown rising t sd 150 c hysteresis t sd(hys t ) 25 c www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 4 of 32 parameter symbol test conditions /comments min typ max unit power good pgood high, fb rising threshold 5 89 92 95 % pgood low, fb rising threshold 5 1 11 1 15 118 % pgood high, fb falling threshold 5 106 109 112 % pgood low, fb falling threshold 5 83 86 89 % pgood delay t pgood 50 s high leakage current i pgood(src) v pgood = v cc 1 10 a pull - down resistor i pgood(snk) fb = 0 v 0.5 0. 7 k? trk trk input voltage range 0 600 mv trk to fb offset voltage trk = 0 mv to 500 mv 10 mv 1 guaranteed by design. 2 measured between vin and sw pins includes bond wires and pin resistance. 3 based on bench characterization. measured with v in = 12 v, v out = 1.2 v , load = 1 a, f sw = 1 mhz, and the output in regulation. measurement does not include dead time. 4 based on bench characterization. measured with v in = 15 v, v out = 12 v , load = 1 a, f sw = 600 khz, and the output in regulation. measurement does not include dead time. 5 this threshold is expressed as a percentage of the nom inal output voltage. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 5 of 32 absolute maximum rat ings table 2 . parameter rating vin to p gnd ? 0.3 v t o + 40 v en to agnd ? 0.3 v to + 40 v sw to pgnd ? 0. 3 v to + 40 v bst to pgnd ? 0.3 v to +4 5 v vcc to agnd ? 0.3 v to +6 v bst to sw ? 0.3 v to +6 v freq , pgood, ss/trk, comp, fb to agnd ? 0.3 v to +6 v pgnd to agnd 0.3 v operating junction temperature range ? 40c to + 1 25c storage temperature range ? 65c to + 1 50c lead temperature (soldering, 10 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional o peration of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resist ance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages , and is based on a 4 - layer standard jedec board. table 3 . thermal resistance package type ja jc unit 12- lead lfcsp 40 2.4 c/w esd caution www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 6 of 32 pin configuration an d function descripti ons fb com p notes 1. the exposed p ad should be connected t o the system agnd plane and pgnd plane. en vin sw pgnd pgood freq ss/trk agnd vcc bst 10581-003 9 8 7 1 2 3 4 5 6 12 1 1 10 t op view ADP2441 figure 3. pin configuration , top view table 4 . pin function descriptions pin n o. nemonic description 1 fb feedback r egulation voltage is 0.6 v . connect this pin to a resistor divider from the output of the dc -to - dc regulator . 2 comp error amplifier compensation . connect a resistor and capacitor in series to ground. 3 en precision enable . this features offers 5 % ac curacy when using a 1.25 v reference voltage. pull this pin high to enable the regulator and low to disable the regulator . 4 pgood active high power - good output. this pin is pulled low when the output is out of regulation. 5 freq switching frequency. a resistor to agnd sets the switching frequency (see the setting the switching frequency section ) . 6 ss /trk soft start /tracki ng input . a capacitor to ground is required to program the soft start time, which graduall y ramps up the output. a resistive divider to an external reference is required on this pin to track an external voltage. 7 pgnd power ground . connect a decoupling ceramic capacitor as close as possible between the vin pin and this pi n. connect this pin directly to the exposed pad . 8 sw switch. the midpoint for the drain of the l ow - side n - channel power mosfet switch and the source for the high - side n - channel power mosfet switch. 9 vin power supply input . connect this pin to the input power source , and connect a bypass ceramic capacitor directly from this pin to p gnd , as close as possible to the ic. the operation voltage is 4.5 v to 36 v . 10 bst bo ost. con nect a 10 nf ceramic capacitor between the bst and sw pins as close to the ic as possible to form a floating supply for the high - side n - channel power mosfet driver. this capacitor is needed to drive the gate of the n - channel power mosfet above the supply voltage. 11 vcc output of the internal low dropout regulator. this pin s uppl ies power for the inte rnal controller and driver circuitry. connect a 1 f ceramic capacitor between vcc and agnd and a 1 f ceramic capacitor between vcc and pgnd. the vcc output is active when the en pin voltage is more than 0.7 v. 12 agnd analog ground . this pin is the i nte rnal ground for the control functions. connect this pin directly to the exposed pad. ep exposed thermal pad. the exposed pad should be c onnect ed to agnd and pgnd . www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 7 of 32 typical performance characteristics 0 20 40 60 80 100 10 30 50 70 90 0.01 0.1 load (a) 1 efficienc y (%) v in = 5v v in = 2 4 v v out = 3.3v f sw = 300khz coilcraft mss1038 v in = 1 2 v 10581-004 figure 4 . efficiency vs . load current, v out = 3.3 v , f sw = 300 k hz 0 20 40 60 80 100 10 30 50 70 90 0.01 0.1 1 efficienc y (%) load (a) v in = 12v 10581-006 v in = 24v v in = 36v v out = 5v f sw = 300khz coilcraft mss1038 figure 5 . efficiency vs. load current, v out = 5 v , f sw = 300 k hz 0 20 40 60 80 100 10 30 50 70 90 0.01 0.1 1 efficienc y (%) load (a) v in = 24v 10581-008 v in = 36v v out = 12v f sw = 300khz coilcraft mss1038 figure 6 . efficiency vs. load current, v out = 12 v , f sw = 300 k hz 0 20 40 60 80 100 10 30 50 70 90 0.01 0.1 1 efficienc y (%) load (a) v in = 5v v in = 1 2 v v in = 2 4 v v out = 3.3v f sw = 700khz coilcraft mss1038 10581-005 figure 7 . efficiency vs. load current, v out = 3.3 v , f sw = 700 k hz 0 20 40 60 80 100 10 30 50 70 90 0.01 0.1 1 efficienc y (%) load (a) v in = 12v 10581-007 v in = 36v v out = 5v f sw = 700khz coilcraft mss1038 v in = 24v figure 8 . efficiency vs. load current, v out = 5 v , f sw = 700 k hz 0 20 40 60 80 100 10 30 50 70 90 0.01 0.1 1 efficienc y (%) load (a) 10581-009 v out = 12v f sw = 600khz coilcraft mss1038 v in = 24v v in = 36v figure 9 . efficiency vs. load current, v out = 12 v , f s w = 600 k hz www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 8 of 32 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 0.2 0.4 0.6 0.8 1.0 v out error (%) load (a) v in = 12v v in = 24v v in = 36v v out = 5v f sw = 700khz 10581-010 figure 10 . load regulation for different suppl ies ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 0.2 0.4 0.6 0.8 1.0 v out error (%) load (a) t a = ?40c t a = +25c t a = +125c 10581-0 1 1 v in = 24v v out = 5v f sw = 700khz figure 11 . load regulation for different tempera t ures ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 7 12 17 22 27 32 37 v out error (%) v in (v) l oa d = 500 m a l oa d = 1 a 10581-012 v in = 24v v out = 5v f sw = 700khz figure 12 . line regulation , v out = 5 v for different loads 0 50 100 150 200 250 300 350 400 5 10 15 20 25 30 35 40 p skip threshold load current (ma) v in (v) f sw = 3 00khz f sw = 7 00khz v out = 3.3v 10581-013 figure 13 . pulse skip threshold , v out = 3.3 v 0 50 100 150 200 250 300 10 15 20 25 30 35 40 p skip threshold load current (ma) v in (v) f sw = 7 00khz 10581-014 v out = 5v f sw = 3 00khz figure 14 . pulse skip threshold, v out = 5 v 0 50 100 150 200 250 300 15 20 25 30 35 40 p skip threshold load current (ma) v in (v) f sw = 3 00khz f sw = 600khz 10581-015 v out = 12v figure 15 . pulse skip threshold , v out = 12 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 9 of 32 0 2 4 8 6 10 12 ?50 0 50 100 150 shutdown curent (a) temper a ture (c) v in = 36v v in = 4.5v 10581-017 figure 16 . shutdown current vs. temperature uvlo threshold (v) temper a ture (c) 10581-018 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ?50 ?25 0 25 50 75 100 125 u v l o, ri s in g v in u v l o, f a lli n g v in figure 17 . uvlo threshold vs. tempe rature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 fb (v) track (v) 10581- 1 18 figure 18 . tracking range 0.05 0.25 0.45 0.65 0.85 1.05 1.25 1.45 1.65 1.85 2.05 2.25 ?50 ?30 ?10 10 30 50 70 90 1 10 130 150 supp l y current (ma) temper a ture (c) v in = 36v v in = 24v v in = 12v v in = 4.5v 10581-016 figure 19 . supply current vs. temperature 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 ?50 ?30 ?10 10 30 50 70 90 1 10 130 150 enable vo lt age (v) temper a ture (c) en ab l e ri si n g t h re sh o l d en ab l e f alli ng t h re sh o l d 10581-019 figure 20 . enable threshold vs. temperature 60 70 80 90 100 110 120 130 ?50 ?30 ?10 10 30 50 70 90 110 130 150 pgood threshold (%) temperature (c) p good rise, fb increasing p good fall, fb increasing p good rise, fb decreasing p good fall, fb decreasing 10581-021 figure 21 . pgood threshold vs. temperature www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 10 of 32 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 35 40 switching frequenc y (khz) v in (v) f sw = 300khz f sw = 1mhz f sw = 700khz 10581-022 figure 22 . switching frequency vs. supply 0 25 50 75 100 125 150 175 200 ?50 ?30 ?10 10 30 50 70 90 1 10 130 150 on time and off time (ns) temper a ture (c) mi n imum o n mi n imum o f f 10581-024 figure 23 . minimum on tim e and minimum off time vs. temperature 100 120 140 160 180 200 220 240 260 ?50 ?25 0 25 50 75 100 125 150 high-side r ds(on) (m?) temper a ture (c) 10581-027 fi gure 24 . high - side r ds ( on ) vs. te mperature 200 300 400 500 600 700 800 900 1000 1 100 1200 ?50 ?30 ?10 10 30 50 70 90 1 10 130 150 frequenc y (khz) temper a ture (c) f sw = 30 0 khz f sw = 1mhz f sw = 7 00khz 10581-023 figure 25 . switching frequency v s. temperature 1.50 1.52 1.54 1.56 1.58 1.60 1.62 1.64 1.66 1.68 1.70 1.72 1.74 1.76 1.78 1.80 ?50 0 50 100 150 current (a) temper a ture (c) v in = 36v v in = 4.5v 10581-126 figure 26 . current limit vs. temperatu re 0 20 40 60 80 100 120 140 160 180 ?50 ?30 ?10 10 30 50 70 90 1 10 130 150 lo w -side r ds(on) (m?) temper a ture (c) 10581-026 figure 27 . low - side r ds(on) vs. temperature www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 11 of 32 10581-028 ch1 20.0mv b w ch2 10.0v ch4 200ma ? m4.00s a ch4 120ma 1 4 2 t 41.40% v in = 24v v out = 3.3v f sw = 500khz v out inductor current sw figure 28 . pulse skip mode, v in = 24 v, v out = 3.3 v, f sw = 500 khz, no load 10581-030 ch1 20.0mv b w ch2 10.0v ch4 500ma ? m1.00s a ch2 9.80v 1 4 2 t 41.40% v out inductor current sw v in = 24v v out = 3.3v f sw = 500khz load = 1a figure 29 . pwm mode , v in = 24 v, v out = 3.3 v , f sw = 500 khz, load = 1 a 10581-032 ch1 100mv b w ch2 10v ch4 500ma ? m200s a ch4 690ma 1 4 2 t 79.80% v out load sw v in = 24v v out = 5v f sw = 700khz load step = 500ma figure 30 . load transient response , v in = 24 v, v out = 5 v, f sw = 7 00 khz, load step = 500 ma 10581-029 ch1 20.0mv b w ch2 10.0v ch4 500ma ? m4.00s a ch4 120ma 1 4 2 t 41.40% v in = 24v v out = 3.3v f sw = 500khz load = 100ma v out inductor current sw figure 31 . pulse skip mode , v in = 24 v, v out = 3.3 v, f sw = 500 khz, load = 100 ma 10581-031 ch1 200mv b w ch2 10.0v ch4 1.00a ? m2.00ms a ch1 60.0mv 1 4 2 t 49.40% v out inductor current sw figure 32 . hiccup mode , v in = 24 v, v out = 3.3 v, f sw = 500 khz, output short to pgnd 10581-033 ch1 50.0mv b w ch2 10.0v ch4 200ma ? m200s a ch4 604ma 1 4 2 v out load sw v in = 24v v out = 5v f sw = 700khz load step = 300ma figure 33 . load transient response , v in = 24 v, v out = 5 v, f sw = 7 00 khz, load step = 300 ma www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 12 of 32 10581-034 ch1 100mv b w ch2 5.00v ch4 500ma ? m200s a ch4 690ma 1 4 2 v out load sw v in = 12v v out = 5v f sw = 300khz load step = 500ma figure 34 . load transient response , v in = 12 v, v out = 5 v, f sw = 3 00 khz, load step = 500 ma 10581-035 ch1 200mv b w ch2 10.0v ch4 500ma ? m200s a ch4 550ma 1 4 2 v out load sw v in = 24v v out = 12v f sw = 300khz load step = 500ma figure 35 . load transient response , v in = 24 v, v out = 12 v, f sw = 3 00 khz, load step = 500 ma 10581-036 ch1 2.00v b w ch4 2.00v ch3 2.00v m1.00ms a ch3 1.64v 3 1 4 v out pgood enable v in = 24v v out = 5v f sw = 700khz fig ure 36 . power go od s tartup , v in = 24 v, v out = 5 v, f sw = 700 khz 10581-037 ch1 200mv b w ch2 10.0v ch4 500ma ? m200s a ch4 600ma 1 4 2 v out load sw v in = 24v v out = 12v f sw = 600khz load step = 500ma figure 37 . load transient response , v in = 24 v, v out = 12 v, f sw = 6 00 khz, load step = 500 ma 10581-038 ch1 2.00v b w ch4 2.00v ch3 5.00v m 200s a ch3 1.60v 3 1 4 v out pgood enable v in = 24v v out = 5v f sw = 700khz figure 38 . power - go od s h utdown , v in = 24 v, v out = 5 v, f sw = 700 khz 10581-039 ch1 2.00v b w ch2 10.0v b w ch3 10.0v m4.00ms a ch3 5.00v 3 1 2 v out v in sw v in = 36v v out = 5v f sw = 700khz figure 39 . startup with v in , v in = 36 v, v out = 5 v, f sw = 7 00 khz , no load www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 13 of 32 10581-040 ch1 2.00v b w ch2 10.0v b w ch3 10.0v m4.00ms a ch3 9.00v 3 1 2 v out v in sw v in = 36v v out = 5v f sw = 700khz load = 5? figure 40 . startup w ith v in , v in = 36 v, v out = 5 v, f sw = 7 00 khz , load = 5 ? 10581-041 ch1 2.00v b w ch2 10.0v ch4 2.00v ch3 5.00v m200s a ch3 2.20v 3 1 2 4 v out enable ss sw v in = 24v v out = 5v f sw = 700khz load = 5? figure 41 . shutdown with precision enable, v in = 24 v, v out = 5 v, f sw = 7 00 khz , load = 5 ? 10581-042 ch1 2.00v b w ch2 10.0v ch4 500mv ch3 5.00v m2.00ms a ch3 2.20v 3 1 2 4 v out enable ss sw v in = 24v v out = 5v f sw = 700khz load = 5? ss = 10nf figure 42 . startup with precision enable, v in = 24 v, v out = 5 v, f sw = 7 00 khz , load = 5 ?, ss = 10 n f 10581-143 ch1 2.00v b w ch2 10.0v ch4 2.00v ch3 5.00v m1.00ms a ch3 1.40v 3 1 2 4 v out enable ss sw v in = 24v v out = 5v f sw = 700khz figure 43 . soft start startup with precision enable, v in = 24 v, v out = 5 v, f sw = 7 00 khz , no load , internal ss ?90 ?50 ?10 30 70 1 10 ?70 ?30 10 50 90 1 10 100 magnitude (db) ?200 ?120 ?40 40 120 200 ?160 ?80 0 80 160 phase (degrees) frequenc y (khz) crossover = 58khz: 1/12 f sw phase margin = 55 v in = 24v v out = 5v f sw = 700khz load = 1a 10581-144 figure 44 . magnitude and phase vs. frequency www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 14 of 32 internal block diagr am vin power stage uvlo internal ldo vcc bst state machine gate control logic en + 1.25v fb i ss + + ? v ref = 0.6v ss/trk sw pgnd nmos nmos slope compensation/ ramp generator current-limit comparator current sense amplifier reference current band gap reference pwm comparator freq osc hiccup timer comp threshold pulse skip enable clock enable v cc comp 1v pwm hiccup + + ? agnd 115% of feedback pgood v fb 86%of feedback + ? 10581-043 figure 45 . block diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 15 of 32 theory of operation the ADP2441 is a fixed frequency, current mode control , step - down , synchronous switching regulator that is capable of driving 1 a loads. the devic e operate s with a wide input voltage range from 4.5 v to 36 v , and its output is adjustable from 0.6 v to 0. 9 v v in . the integrated high - side n - channel power mosfet and the low - side n - channel power mosfet yield high efficiency with me dium to h eavy load s. pulse skip mode is available to improve efficiency at light loads . the ADP2441 includes programmable features, such as soft start, output voltage, switching frequency , and power good . these features are progr amm e d externally via tiny resistor s and capacitor s. t he ADP2441 also includes protection features , such as uvlo with hysteresis, output short - circuit protection , and thermal shutdown . control architecure the ADP2441 is based on the emulated peak current mode control architecture . fixed frequency mode a basic block diagram of the control architecture is shown in figure 46. with medium to h eavy load s, the ADP2441 operates in the fixed switching frequency pwm mode. the o utput voltage, v out , is sensed on the feedback pin, fb. an error amplifier integrates the error between the feedback voltage and the reference voltage ( v ref = 0.6 v) to generate an error voltage at the co mp pin . a cur rent sense a mplifier senses the valley inductor current ( i l ) during the off period when the low - side power mosfet is on and the high - side power mosfet is off. an inter nal oscillator initiate s a pwm pulse to turn off the low - side power mosfet and turn on the high - side p ower mosfet at a fixed switching f requency . when the high - side n - channel power mosfet is enabled, the valley inductor current information is added to an e mulated ramp signal , and then the pwm comparator compare s this value to the error voltage on the comp pin . the output of the pwm comparator modulates the duty cycle by adjusting the trailing edge of the pwm pulse that turns off the high - side power mosfet a nd turns on the low - side power mosfet . slope compensation is p rogrammed internally into the emu lated ramp signal and is automatically selected, depending on the input voltage , output voltage , and switching frequency. this prevents sub harmonic oscillations for near or greater than 50% duty cycle operation. the one restriction o f this f eature is that the inductor ripple c urrent must be set b etween 0.2 a and 0.5 a to provide sufficient current information to the loop. comparator s r ref driver clock comp v ramp v fb v out v in pwm i l r swl i l vc sense_ out q qb ramp emulation block g cs g m 10581-044 figure 46 . cont rol architecture block diagram p ulse s kip mode the ADP2441 has built - in pulse skip circuitry that turns on during light loads, switching only as necessary so that the output voltage remains within regul ation. this allo ws the regulator to maintain high efficiency during operation with l ight load s by reducing switching losses. the pulse skip circuitry includes a comparator, which compares the comp voltage to a fixed pulse s kip threshold . com p contro l logic ADP2441 pulse ski p threshold 1v dc 10581-045 figure 47 . pulse skip comparator with light load s , the output voltage discharges at a very slow rate (load dependent). when the output voltage is within regulation , the device enter s sleep mode and draw s a very small quiescent current. as the output volt ag e dro ps belo w the regulation voltage , the comp voltage rises above the pulse skip threshold. the device wakes up and starts switching until the output voltage is within regulation. as the load increases , the settlin g value of the co mp voltage increases. at a particular load, comp settles above the pulse skip threshold , and the part enters the fixed frequency pwm mode. therefore, the load current at which comp exceeds the pulse skip threshold is defined a s the pulse skip current threshold ; the value varies wit h the duty cycle and the inductor ripple c urrent. the measured value of pulse skip threshold over v in is given in figure 13, figure 14 , and figure 15. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 16 of 32 adjustable frequency the ADP2441 features a programmable oscillator frequency with a resistor connected between the freq and agnd pins . at power - up , the freq pin is forced to 1.2 v a nd current flows from the freq pin to agnd ; the c urrent value is based on the resistor value on the freq pin. then , the same current is replicated in the oscillator to set the switching frequency. note that the resistor connected to the freq pin s hould be placed as close as possible to th e freq pin ( see t he applications information section for more information) . power good the pgood pin is an open - drain output that indicate s the status of the output voltage . when th e voltage of the fb pin is between 92% and 109 % of the internal reference voltage , the pgood output is pulled high , provided there is a pull - up resistor connected to the pin. when the voltage of the fb pin is not within this range , the pgood output is pull ed low to a gnd. the pgood threshold is shown in figure 48. likewise , the pgood pin is pulled low to a gnd when the input voltage is below the internal uvlo threshold, when the en pin is low, or when a thermal shutdo wn event has occurred. % of v out set % of v out set v out rising v out falling 110 90 116 84 power good overvolage undervoltage pgood undervoltage power good 100 100 10581-047 figure 48 . pgood threshold in a typical application, a pull - up resistor connected between the pgood p in and an external supply is used to generate a logic signal. this pull - up resistor should rang e in valu e from 3 0 k? to 1 00 k ? , and the external supply should be less than 5.5 v . soft start the ADP2441 soft start feature allows the output voltage to ramp up in a controlled manner, limiting the inrush current during startu p. an external capacitor connected between the ss /trk and agnd pins is required to program the soft start time. the programmable soft start feature is useful when a load requires a controlled voltage slew rate at startup. when the regulator powers up and s oft start is enabled, the internal 1 a current source charges the external soft start capacitor, establishing a voltage ramp slope at the ss pin, as shown in figure 49 . the soft start period ends when the soft start ramp voltage exceeds the intern al reference of 0 . 6 v. the ADP2441 also features an internal default soft start time of 2 ms. for more information, see the applications information section. 10581-149 ch1 2.00v b w ch2 1.00v ch3 5.00v m10.0ms a ch1 2.52v 3 1 2 v out enable ss v in = 24v v out = 5v f sw = 700khz load = 1a external ss = 10nf figure 49 . exte rnal soft start tracking the ADP2441 has a tracking feature that allows the output voltage to track an external voltage. this feature is especially useful in a system where power supply sequencing and trackin g is required. the ADP2441 ss/ trk pin is connected to the internal error amplifier. the internal error amplifier includes three inputs: the internal reference voltage, the ss / trk voltage, and the feedback vol tage. the error amplifier regulates the feedback voltage to the lower of the other two vol tages. to track a master voltage, tie the ss/ trk pin to a resistor divider from the master voltage as shown in figure 50. master voltage comp ref ss/trk sw fb ADP2441 r trk_top r trk_bot r top v out r bottom 10581-048 figure 50 . tracking feature block diagram the ratio of the slave output voltage to the master voltage is a function of the two dividers as follows: ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = bot trk top trk bottom top master out r r r r v v _ _ 1 1 ( 1 ) www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 17 of 32 coincident tracking the most common mode of tracking is coincident trac king . i n this method , the slope of the slave voltage matches that of the master voltage , as shown in figure 51. as the master voltage rises, the slave voltage rises identically. eventually, the slave voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the ss/ trk input continues to increase , thus preventing itself from influencing the output voltage . voltage (v) time master voltage slave voltage 10581-049 figure 51 . coincident tracking for c oincident tra ck in g, select resistor values such that r trk _t op = r top and r trk _b ot = r bot tom in equation 1. ratiometric tracking in th e ratiometric tracking scheme, the master and the slave voltages rise with different slope s . voltage (v) time master voltage slave voltage 10581-050 figure 52 . rati ometric tracking for r atiometric track ing in which the master voltage rises faster than the slave voltage (a s shown in figure 52) , select r trk _t op r top and r trk _b ot = r bot tom in equation 1. undervoltage lockout ( uvlo ) the uvlo function prevents the ic from turning on while the input voltage is below the specified operating range to avoid an undesired operating mode. if the input voltage drops below the specified range, the uvlo function shuts off the device. the rising input voltage threshold for the uvlo function is 4.2 v with 200 mv hysteresis. the 200 mv of hysteresis prevent s the regulator from turning on and off repeatedly with slow voltage ramp on the vin pin . precision enable/ shutdown the ADP2441 features a precision enable pin (en) that can be used to enable or shut down the device. the 5 % accuracy lends itself to using a resistor divider from the vin pin (or an other external supply) to program a desired uvlo threshold that is higher than the fixed internal uvlo of 4. 2 v. the hysteresis is 1 0 0 m v. if a resistor divider is not used , a logic signal can be applied. a l ogic high enable s the part, and a logic low force s the part into shutdown mode. vin en freq agnd comp sw ADP2441 r1 r2 v out v in bst fb 10581-051 figure 53 . precision enable used as a programmable uvlo current - limit and short - circuit protection the ADP2441 has a current - limit comparator that compare s the current sensed across the low - side p ower mosfet to the internally set reference current. if the sensed current exceeds the reference current , the high - side power mos fet is not turned on in the next cycle and the low - side power mosfet stays on until the inductor current ra mps down below the c urrent - limit level. if the output is overloaded and the peak inductor current exceeds the preset current limit for more than eight consecutive clock cycles, the hiccup mode current - limit condition occurs. the output goes to sleep for 6 ms, during which tim e the output is discharge d , the average power dissipation is reduced, and the part wakes up with a so ft start period. if the current - limit condition is triggered again, the output goes to sleep and wakes up after 6 ms. figure 32 s hows the current - limit hiccup mode when the output is shorted to pgnd . thermal shutdown if the ADP2441 junction temperature rises above 150c , the thermal shutdown circuit turns off the switching regulator. ex treme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. a 25c hysteresis is included so that when a thermal shutdown occurs, the ADP2441 does not return to normal operation until the junction temperat ure drops below 125c. soft start is active up on each restart cycle. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 18 of 32 applications informa tion selecting the output voltage the output voltage is set using a resistor divider connected betw een the output voltage and the fb pin (see figure 54) . the resistor divider divides down the output voltage to the 0.6 v fb regulation voltage. the output voltage can be set to as low as 0.6 v and as high as 90% of the power input voltage. the ratio of the resistive voltage divider sets the output voltage, and the absolute value of the resistors sets the divider string current. for lower divi der string currents, the small 5 0 na (0.1 a maximum) fb bias current shoul d be taken into account when calculating the resistor values. the fb bias current can be ignored for a higher divider string current ; however , using small feedback resistors degrades efficiency at very light loads. t o limit degradation of the output volta ge accuracy due to fb bias current to less than 0.0 0 5% (0.5% maximum), ensure that the divider string current is greater than 20 a. to calculate the desired resistor values, first determine the value of the bottom resistor, r bottom , as follows: string ref bottom i v r = ( 2 ) w here: v ref is the internal refe rence and equals 0.6 v. i string is the resistor divider string current. then calculate the value of the top resistor, r top , as follows: ? ? ? ? ? ? ? ? ? = ref ref out bottom top v v v r r ( 3 ) ADP2441 fb r t op r freq c ss v out r bot t om pgood externa l supp l y freq ss/trk 10581-052 figure 54 . voltage divider table 5 . ou tput voltage selection voltage (v) r top (k ? ) r bottom (k ? ) 12 190 10 5 73 10 3.3 45 10 1.2 10 10 setting the switching frequency the choice of the switching frequency depends on the required dc - to - dc conversion ratio and is limited by the minimum and maximum controllable duty cycle, as shown i n figure 55 . this is due to the requirement of minimum on time and minimum off time for current sensing and robust operation . however, the choice is also influenced by whether there is a need for small external co mponents. for example, for small, ar ea limited power solutions, higher switc hing frequencies are required . 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 dut y cycle (%) frequenc y (khz) d max d min 10581-155 figure 55 . duty cycle vs. switching frequency calculate th e value of the frequency resistor using the following equation: sw freq f r 500 , 92 = ( 4 ) where r freq is in k? , and f sw is in kh z. ta ble 6 and figure 56 provide examples of frequency resistor values, which are based on the switching frequency . ta ble 6 . frequency resistor selection r freq (k?) frequency 308 300 khz 132 700 khz 92.5 1 mhz 10581-053 200 300 400 500 600 700 800 900 1000 1 100 1200 50 100 150 200 250 300 350 frequenc y (khz) resis t $1&(n? figure 56 . frequency vs. resistance www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 19 of 32 soft start the soft start function limits the input inrush current and prevents output overshoot at startup . the soft start time is program m ed by connecting a small ceramic capacitor between the ss /trk and agnd pi ns , with the value of this capacitor defin ing the soft start time, t ss , as follows: ss ss ss ref c i t v = ( 5 ) where : v ref is the internal reference voltage and equals 0.6 v. i ss is the soft start current and eq uals 1 a. c ss is the soft start capacitor value. table 7 . soft start time selection soft start capacitor (nf) soft start time (ms) 5 3 10 6 20 12 alternatively, t he user can float the ss/trk pin and use the internal soft start time of 2 ms. external components selection input capacitor selection the input current to a buck regulator is pulsating in nature. the current is zero when the high - side switch is off and is approxi - mately equal to the load current when the switch is on. beca use switching occurs at reasonably high frequencies (300 khz to 1 mhz), the input bypass capacito r usually supplies m ost of the high frequency current (ripple current), allowing the input power source to supply only the average (dc) current . the input cap acitor needs a sufficient ripple current rating to handle the input ripple and needs an esr that is low enough to mitigate the input voltage ripple . in many cases , different types of capacitors are placed in parallel to minimize the effective esr and esl. the minimum input capacitance required for a particular load is sw esr out pp out min in f r d i v d d i c ) ( ) 1 ( _ ? ? = ( 6 ) where: v pp is th e desired input ripple voltage. r esr is th e equivalent series resistance of the capacitor. i out is the maximum load current . it is recommended to us e a ceramic bypass capacitor because the esr associated with this type of capacitor is near zero , simplifying the equation to sw pp out min in f v d d i c ? = ) 1 ( _ ( 7 ) i n addition , i t is recommended to use a ceramic capacitor with a voltage rating that is 1.5 times the input voltage with x5r and x7r dielectric s. using y5v and z5u dielectrics is not recommended due to their poor temperature and dc bias characteristics. table 10 shows a li st of recommended mlcc capacitors from mu rata and taiyo yuden. for large step load transients , add more bulk capacitance by , for example, using electrolytic or polymer capacitors. make sure that the ripple current rating of the bulk capacitor exceeds the minimum input ripple current of a parti cu lar design. inductor selection the high switching frequency of the ADP2441 allows for minimal output voltage ripple even when small inductors are used . selecting t he siz e of the inductor involves considering the trade - off between efficiency and transient response. a small er inductor results in larger inductor current ripple , which provides excellent transient response but degrades efficiency. due to the high switching fre quency of the ADP2441 , using shielded ferrite core indu ctors is recommended because of their low core losses and low emi. the inductor ripple current also affects the stability of the loop because the ADP2441 uses the emulated peak current mode architecture. in the traditional approach of slope compensation, the user sets the inductor ripple current and then set s the slope compensation using an external ramp resistor. i n most cases , the inductor rippl e current is typically set to be 1/3 of the maximum load current for optimal transient response and efficiency. the ADP2441 has internal slop e c ompensation , which assumes that the inductor ripple current is se t to 0.3 a (30% of t he maximum load of 1 a) , eliminat ing the need for an external ramp resistor. for the ADP2441 , choose an inductor such that the peak - to - peak ripple current of the inductor is between 0.2 a a nd 0.5 a for stable operation. therefore, calculate the inductor value as follows: l f v v v v i sw in out in out l ? = ? ) ( ( 8 ) 0.2 a i l 0.5 a sw in out in out sw in out in out f v v v v l f v v v v ? ? ) ( 5 ) ( 2 sw in out in out ideal f v v v v l ? = ) ( 3 . 3 ( 9 ) where : v in is the input voltage. v out is the desired output voltage. f sw is the regulator switching frequency . for applications with a wide input (v in ) range , choose the inductor bas ed on the geometric mean of the input voltage extremes . min in max in geometric in v v v _ _ ) ( = where: v in _max is the maximum input voltage. v in _min is the m inimum input voltage . www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 20 of 32 the i nductor value is based on v in (geometric) as follows: sw geometric in out geometric in out ideal f v v v v l ? = ) ( ) ( ) ( 3 . 3 table 8 . inductor value s for vario us v in , v out , an d f sw combinations inductor value f sw ( k hz ) v in (v) v out (v) min (h ) max ( h ) 300 12 3.3 22 27 300 12 5 27 33 300 24 3.3 27 33 300 24 5 39 47 300 24 12 56 68 300 36 3.3 27 33 300 36 5 39 47 300 36 12 68 82 600 12 3.3 12 15 600 12 5 15 18 600 24 3.3 15 18 600 24 5 18 22 600 24 12 27 33 600 36 3.3 15 18 600 36 5 22 27 1000 12 5 6.8 10 1000 24 5 10 12 1000 24 12 18 22 1000 36 5 12 15 t o avoid inductor saturation and ens ure proper operation, choose the inductor value so that neither the saturati on current nor the max imum temp erature rated current ratings are exceeded. inductor manufacturers specify both of th ese ratings in data s heets , or the ratin g can be calculated as follows : 2 ) ( _ l max load peak l i i i ? + = (1 0 ) where : i loa d ( max ) is the ma ximum dc load current. i l is the peak - to - peak inductor ripple current . table 9 . recommended induc tors value ( h ) small size inductor s (< 10 mm 10 mm ) large size i nductors (> 10 mm 10 mm ) 10 xal 404 0 - 103me mss1260 18 lps6235 - 183ml mss1260 33 lps6235 - 33ml mss1260 15 xal4 0 4 0 - 153 me mss1260 output capacitor selection the output capacitor selection affects both the output voltage ripple and the loop dynamics of t he regulator . t he ADP2441 is designed to operate with small ceramic output capacitors that have low esr and esl; therefore, the device can easily meet tight output voltage ripple specifications. for best p erformance, u se x5r or x7r dielectric capacitors with a voltage rating that is 1.5 times the output voltage and avoid using y5v and z5u dielectric capacitors , which have poor temperature and dc bias characteristics. table 10 lists some recommended capacitor from murata an d taiyo yuden. for acceptable maximum output voltage ripple, determine the minimum output capacitance, c out(min) , as follows: ? ? ? ? ? ? ? ? + ? ? ? ) ( 8 1 min out sw l ripple c f esr i v ( 1 1 ) therefore, ) ( 8 ) ( esr i v f i c l ripple sw l min out ? ? ? ? ? ( 1 2 ) where: v ripple is the allowable peak - to - peak output voltage ripple. i l is the inductor ripple current. esr is the equivalent series resistance of the capacitor. f sw is the switching frequency of the regulator . if there is a step load requirement , choose the o utput capacitor value based on the value of the step load. for the maximum accep - table output volta ge droop/overshoot cau sed by the step load, ? ? ? ? ? ? ? ? ? ? ? droop sw step out min out v f i c 3 ) ( ) ( ( 1 3 ) where: i out( step ) is the load step. f sw is the switching frequency of the regulato r . v dro o p is the maximum allowable output voltage droop/overshoot. select the largest outpu t capacitance given by equation 1 2 and equation 1 3 . when choosing the type of ceramic capacitor for the output filter of the regulator , select one with a nominal ca pacitance that is 20% to 30% larger than the calculated value because the effective capacitance de gra des with dc voltage and temperat ure . figure 57 shows the capac itance loss due to the output voltage dc bias for t hree x 7 r mlcc capacitors from murata. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 21 of 32 0 30.0 24.6 19.2 13.8 8.40 3.00 5 10 dc bias vo lt age (v) ca p aci t ance (f) 15 20 25 22f/25v 10f/25v 10581-157 figure 57 . capacitance vs . dc bias voltage for example, to attain 20 f of o utput capacitance with an output voltage of 5 v while pro viding some margin for temperature variation , use a 22 f capacitor with a voltage rating of 25 v and a 10 f capacitor with a voltage rating of 25 v in parallel . this configuration ensure s that the output capacitance is sufficient under all conditions and, therefore, th at the device exhibits stable behavior. table 10. recommended output capacitor s for ADP2441 vendor ca pacitor murata taiyo yuden 10 f/25 v grm32dr71e106ka12l tmk325b7 106 k n - t r 22 f/25 v grm32er71e226ke15l tmk325b7226mm - tr 47 f/6.3 v gcm32er70j476ke19l jmk325b7476mm - tr 4.7 f/50 v grm31cr71h475ka12l umk325b7475mmt boost capacitor the boost pin (bst) is used to power up the internal driver for the high - side power mosfet . in the ADP2441 , the high - side power mosfet is an n - channel device to achieve high efficiency in mid and high duty cycle application s. to power up the high - side driver , a capacitor is required between the bst and sw pin s. th e size of this boost capacitor is critical because it affects the light load functionality and efficiency of the device . therefore, i t is strongly recommended to use a 1 0 nf ceramic boost capacitor with a voltage rating of 50 v between the bst and sw pins and to place the capacitor as close as possible to the ic. vcc capacitor the ADP2441 has an internal regulator to power u p the internal controller and the low - side driver. the vcc pin is the output of the internal regulator. the internal regulator provides the pulse current when the low - side driver turns on. therefore , it is recom - mended that a 1 f ceramic capacitor be plac ed between the vcc and pgnd pins as close as possible to the ic and that a 1 f ceramic capacitor be placed between the vcc and agnd pins . loop compensation the ADP2441 uses peak current mode control architect ure for excellent load a nd line transient response. this control architecture has two loops : an external voltage loop and an inner current loop. the inner current loop senses the current in the low - side switch and controls the duty cycle to maintain the a verage inductor current. slope compensation is added to the inner current loop to ensure stable operation when the duty cycle is above 50%. the external voltage loop senses the output voltage and adjusts the duty cycle t o regulate the output v oltage to the desired value . a transconductance amplifier with an external series rc network connected to the comp pin compensates the external voltage loop. ADP2441 vfb g m com p agnd r com p c com p 0.6v 10581-054 figure 58 . rc compensation network large signal an alysis of the loop compensation t he control loop can be broken down into the following three sections: ? v out to v comp ? v comp to i l ? i l to v out pulse-width modulator gm v ref = 0.6v inductor current sense v out v in v comp c comp c out r comp r load ADP2441 i l g m 10581-055 figure 59 . large signal model www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 22 of 32 correspondingly, there are three transfer functions: ) ( ) ( ) ( s z g v v s v s v comp m out ref out comp = ( 1 4 ) cs comp l g s v s i = ) ( ) ( (1 5 ) ) ( ) ( ) ( s z s i s v filt l out = (1 6 ) where : g m is the transcondu ctance of the error amplifier and equals 250 a / v. g cs is the current sense gain and equals 2 a / v. v out is the output voltage of the regulator . v ref is the internal reference volt age and equals 0.6 v. z co mp (s) is the impedance of the rc compensation network that forms a pole at the origin and a zero as expressed in equation 1 7 . comp comp comp comp c s c r s s z + = 1 ) ( (1 7 ) z filt (s) is the impedance of the output filter and is expressed as out load load filt c r s r s z + = 1 ) ( ( 1 8 ) where s is the angular frequency , which can be written as s = 2f. the overall loop gain, h(s), is obtained by multiplying the three transfer functions previously mentioned as follows: ) ( ) ( ) ( s z s z v v g g s h filt comp out ref cs m = ( 19) when the switching frequency ( f sw ), output voltage (v out ), output inductor (l), and output capacitor (c out ) values are selected, the unity crossover frequency can be set to 1 /12 of the switching frequency . at the crossover frequency, the gain of the open - loop transfer function is un ity. h ( f crossover ) = 1 (2 0 ) this yields equation 2 1 for the rc compensation network impedance at the crossover frequency. ref out cs m out crossover crossover comp v v g g c f f z = 2 ) ( (2 1 ) placing s = f crossover in equation 1 7 , comp comp comp c f c r f f z crossover crossover crossover comp + = 2 2 1 ) ( (2 2 ) to ensure that there is sufficient phase margin at the crossover frequency , place th e c ompensator zero at 1/8 of the crossover frequency, as shown in the follow ing equation : 8 2 1 crossover comp zero f c r f comp = (2 3 ) solving equation 2 1 , equation 2 2 , and equation 2 3 yields the value for the resistor and capacitor in the rc compensation network, as shown i n equation 2 4 and equation 2 5 . ref out out cs m crossover comp v v c g g f r = 2 9 . 0 (2 4 ) comp zero comp r f c = 2 1 ( 2 5 ) using these equations allows calculat ing the compensations for the voltage loop. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 23 of 32 design example consider an application with the following specifications: ? v in = 24 v 10% ? v out = 5 v 1% ? switching frequency = 700 k hz ? load = 800 ma typical ? maximum load current = 1 a ? soft start time = 6 ms ? overshoo t 2% under all load transient conditions configuration and co mponents selection resistor divider the first ste p in selec ti n g the external components is to calculat e the resistance of the resistor divider that sets the output voltage. using equation 2 and equation 3 , k 10 a 60 6 . 0 = = = string ref bottom i v r ? ? ? ? ? ? ? ? ? = ref ref out bottom top v v v r r k 3 . 73 v 6 . 0 v 6 . 0 v 5 k 10 = ? ? ? ? ? ? ? ? ? = top r switching frequency cho osing the swit ching frequency involves considering the trade - off between efficiency and component size. low frequency improves the efficiency by reducing the gate losses but require s a large inductor. the choice of high frequency is limited by the minimum and maximum du ty cycle. ta ble 11. duty cycle v in duty cycle 24 v (nominal) d nominal = 20.8% 26 v (10% above nominal) d min = 19% 22 v (10% less than nominal) d max = 23% based on the estimated duty cycle range, choose the switching frequenc y according to the minimum and maximum duty cycle limitations, as shown in figure 55. for example , a 700 khz, frequency is well within the maximum and minimum duty cycle limitations . using equation 4 , sw freq f r 500 , 92 = r freq = 132 k? soft start capacitor for a given soft start time , the soft start capacitor can be calculate d using equation 5 , ss ss ss ref c i t v = ref ss ss ss v t i c = nf 10 v 6 . 0 ms 6 a 1 = = ss c inductor selection select the inductor by using equation 9 . sw in out in out ideal f v v v v l ? = ) ( 3 . 3 h 3 . 18 h 66 . 18 khz 700 v 24 v ) 5 24 ( v 5 3 . 3 = ? = ideal l in equation 9 , v in = 24 v, v out = 5 v, i load( max ) = 1 a , and f sw = 700 khz , which results in l = 1 8.66 h . w hen l = 18 h (the closest standard value) in equation 8 , i l = 0.314 a. although the maximum outpu t current required is 1 a, the maximum peak current is 1.6 a . therefore, the in ductor should be rated for higher than 1.6 a current . input capacitor selection the input filter consist s of a small 0.1 f ceramic capacitor placed as close as possible to the ic. the minimum input capacitance required for a particular load is sw pp out min in f v d d i c ? = ) 1 ( _ where: v pp = 50 mv . i out = 1 a . d = 0.2 3 . f sw = 700 khz . therefore, f 9 . 4 khz 700 v 05 . 0 ) 22 . 0 1 ( 22 . 0 a 1 _ ? = min in c choosing an input capacitor of 10 f with a voltage rating of 50 v ensu re s sufficient capacitance over voltage and temperature. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 24 of 32 output capacitor selection select the outp ut capacitor by using equation 1 2 and equation 1 3 : ) ( 8 ) ( esr i v f i c l ripple sw l min out ? ? ? ? ? equation 1 2 is based on t he output voltage ripple (v ripple ), which is 1% of the o utput voltage . ? ? ? ? ? ? ? ? ? ? ? droop sw step out min out v f i c 3 ) ( ) ( equation 1 3 calculates the capacitor selection based on the transie nt load performance requirement of 2% . p erform these calculations , and the n use the equation that yields the larger capacitor size to select a capacit or . in this example , the values listed in tabl e 12 are substituted for the variables in equation 1 2 and equation 1 3 . tabl e 12. requirements parameter test conditions/comments value ripple current fixed at 0.3 a for the ADP2441 0.3 a voltage ripple 1% of v out 50 mv voltage droop due to load transient 2% of v out 100 mv esr 5 m? f sw 700 khz the calculation based on the output voltage ripple (see equation 1 2 ) dictates that the minimum output capacitance is f 1 . 1 ) m 5 a 3 . 0 mv 50 ( khz 700 8 a 3 . 0 ) ( = ? ? min out c whereas the calculation based on the transient load (see equation 1 3 ) dictates that the minimum output capacitance is f 22 v 1 . 0 khz 700 3 5 . 0 ) ( ? min out c to meet both requirements, use the va lue determined by the latter equation . as shown in figure 57, capacitance degrades with dc bias; therefore, choose a capacitor that is 1.5 times the calculated value. c out = 1.5 2 2 f = 32 f compensation selecti on calculate the compensation component values for the feedback loop by using the following equations : ref out out cs m crossover comp v v c g g f r = 2 9 . 0 comp zero comp r f c = 2 1 selecting the crossover frequency to be 1/12 of the switching frequency and placing the zero frequency a t 1/8 of the crossover frequency ensure s that there is enough phase margin in the system . tab le 13. calculated parameter value parameter test condi tions/comments value f crossover 1/12 of f sw 58.3 khz f zero 1/8 of f crossover 7.3 k hz v ref fixed reference 0.6 v g m trans conductance of error amplifier 250 a/v g cs current sense gain 2 a/v c out output capacitor 22 f v out output voltage 5 v based on the values listed in tab le 13, calculate the compen - sat ion value: ? = k 121 6 . 0 5 22 2 250 3 . 58 2 9 . 0 comp r the closest standard resistor value i s 118 k? . therefore , pf 180 pf 185 118 3 . 7 2 1 = = comp c system configuration configure the system as follows: 1. connect a capacitor of 1 f between th e vcc and pgnd pins and another capacitor of 1 f between the vcc and agnd pins . for best performance, use ceramic x5r or x7r capacitor s with a 25 v voltage rating. 2. connect a ceramic capacitor of 10 nf with a 50 v voltage rating between the bst and sw pin s . 3. connect a resistor between the freq and agnd pins as close as possible to the ic. 4. if using the power - good feature , c onnect a pull - up resistor of 5 0 k ? to an external supply of 5 v . 5. connect a capacitor of 10 nf between the ss and agnd pins . if the tracking feature is need ed, connect a resistor divider between the trk pin and another supply , as shown in figure 50. see figure 60 for a schematic of th is design example and table 14 for the calculated component values. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 25 of 32 typical application circuits design example v in = 24 v 10% , v out = 5 v, f sw = 7 00 khz . v in 24v fb comp en pgood freq ss/trk pgnd vin sw bst agnd vcc ADP2441 v out 5v, 1a c3 1f/25v c4 1f/25v c11 10nf l1 18h r9 132k r7 50k ext pgood trk r5 118k c6 0.1f c7 22f c2 4.7f/ 50v c1 4.7f/ 50v c5 10nf/50v c10 180pf r3 10k c8 10f 10581-057 r2 73.3k figure 60 . ADP2441 typical application circuit , v in = 24 v 10%, v out = 5 v, f sw = 700 khz table 14. calculated component values for figure 60 qty. ref value description part number 2 c1, c2 4.7 f capacitor ceramic, x 7 r , 50 v grm31cr71h475ka12l 2 c3, c4 1 f capacitor ceramic , 1 f , 25 v , x7r , 10% , 0603 grm188r71e105ka12d 2 c5, c 11 10 nf capacitor ceramic , 10, 000 p f , 50 v , 10% , x7r , 603 ecj - 1vb1h103k 1 c7 22 f capacitor ceramic , 22 f , 25 v , x7r , 1210 grm32er71e226k 1 c8 10 f capacitor ceramic , 10 f , 25 v , x7r , 1210 grm32dr71e106ka12l 1 l1 18.3 h inductor, 18.3 h coil craft mss1260t - 183nlb 1 c6 0.1 f capacitor cer amic , 0.1 f , 50 v , x7r , 0805 ecj - 2fb1h104k 1 c10 185 pf capacitor ceramic , 50 v vishay, panasonic 1 r 9 132 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r5 118 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r 2 74 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r3 10 k ? resist or, 1/10 w , 1% , 0603 , smd 1 r7 50 k ? resistor, 1/10 w, 1%, 0603, smd www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 26 of 32 other typical cir c uit configurations v in = 24 v 10%, v out = 12 v, f sw = 600 khz . r7 50k ext v in 24v f sw 600khz fb comp en pgood freq ss/trk pgnd vin sw bst agnd vcc ADP2441 v out 12v, 1a c3 1f/25v c4 1f/25v c11 10nf l1 33.3h r9 154k pgood trk r5 121k c6 0.1f c7 22f/ 25v c2 4.7f/ 50v c1 4.7f/ 50v c5 10nf/50v c10 220pf r3 10k 10581-058 r2 191k figure 61 . ADP2441 typica l application circuit , v in = 24 v 10%, v out = 12 v, f sw = 600 khz table 15. calculated component values for figure 61 qty. ref value description part number 2 c1, c2 4.7 f capacitor ceramic, x 7 r , 50 v grm31cr71h475ka12l 2 c3, c4 1 f capacitor ceramic , 1 f , 25 v , x7r , 10% , 0603 grm188r71e105ka12d 2 c5, c 11 10 nf capacitor ceramic , 10000 p f , 50 v , 10% , x7r , 0603 ecj - 1vb1h103k 1 c7 22 f capacitor ceramic , 22 f , 25 v , x7r , 1210 grm32er71e226k 1 l1 3 3.3 h inductor, 33.3 h coil craft mss1038 - 333ml 1 c6 0.1 f capacitor ceramic , 0.1 f , 50 v , x7r , 0805 ecj - 2fb1h104k 1 c10 220 pf capacitor ceramic , 50 v vishay, panasonic 1 r 9 1 54 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r5 121 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r 2 191 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r3 10 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r7 50 k ? resistor, 1/10 w, 1%, 0603, smd www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 27 of 32 v in = 12 v 10%, v out = 5 v, f sw = 500 khz . r7 50k ext v in 12v f sw 500khz fb comp en pgood freq ss/trk pgnd vin sw bst agnd vcc ADP2441 v out 5v, 1a c3 1f/25v c4 1f/25v c11 10nf l1 18h r9 185k pgood trk r5 118k c6 0.1f c7 22f c8 22f c2 4.7f/ 50v c1 4.7f/ 50v c5 10nf/50v c10 270pf r3 10k 10581-059 r2 73.3k figure 62 . ADP2441 typical application circuit , v in = 12 v 10%, v out = 5 v, f sw = 500 khz table 16. calculated component values for figure 62 qty. ref value description part number 2 c1, c2 4.7 f capacitor ceramic, x7 r , 50 v grm31cr71h475ka12l 2 c3, c4 1 f capacitor ceramic, 1 f , 25 v , x7r , 10% , 0603 grm188r71e105ka12d 2 c5, c 11 10 nf capacitor ceramic, 10, 000 p f , 50 v , 10% , x7r , 0603 ecj - 1vb1h103k 1 c7 22 f capacitor ceramic, 22 f , 25 v , x7r , 1210 grm32er71e226k 1 c8 22 f capacitor ceramic, 22 f , 25 v , x7r , 1210 1 l1 18.3 h inductor, 18.3 h coil craft mss1038 - 183ml 1 c6 0.1 f capacitor ceramic, 0.1 f , 50 v , x7r , 0805 ecj - 2fb1h104k 1 c10 270 pf capacitor ceramic, 50 v visha y, panasonic 1 r 9 185 k ? res istor, 1/10 w , 1% , 0603 , smd 1 r5 118 k ? res istor, 1/10 w , 1% , 0603 , smd 1 r 2 74 k ? res istor, 1/10 w , 1% , 0603 , smd 1 r3 10 k ? resistor, 1/10 w , 1% , 0603 , smd 1 r7 50 k ? resistor, 1/10 w, 1%, 0603, smd www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 28 of 32 v in = 36 v 10%, v out = 3.3 v, f sw = 300 khz . r7 50k ext v in 36v f sw 300khz fb comp en pgood freq ss/trk pgnd vin sw bst agnd vcc ADP2441 v out 3.3v, 1a c3 1f/25v c4 1f/25v c11 10nf l1 33.3h r9 300k pgood trk r5 91k c6 0.1f c7 47f c8 47f c2 4.7f/ 50v c1 4.7f/ 50v c5 10nf/50v c10 560pf r3 10k 10581-060 r2 45k figure 63 . ADP2441 typical application circuit , v in = 36 v 10%, v out = 3.3 v, f sw = 300 khz table 17. calculated component values for figure 63 qty. ref value description part number 2 c1, c2 4.7 f capacitor ceramic, x 7 r , 50 v grm31cr71h475ka12l 2 c3, c4 1 f capacitor ceramic, 1 f , 25 v , x7r , 10% , 0603 grm188r71e105ka12d 2 c5, c 11 10 nf capacitor ceramic, 10, 000 p f , 5 0 v , 10% , x7r , 0603 ecj - 1vb1h103k 1 c7 47 f capacitor ceramic, 47 f , 6.3 v , x7r , 1210 grm32er70j476ke20l 1 c8 47 f capacitor ceramic, 47 f , 6.3 v , x7r , 1210 grm32er70j476ke20l 1 l1 33.3 h inductor, 33.3 h coil craft mss1038t - 333ml 1 c6 0.1 f capa citor ceramic, 0.1 f , 50 v , x7r , 0805 ecj - 2fb1h104k 1 c10 560 pf capacitor ceramic, 50 v vishay, panasonic 1 r 9 300 k ? res istor, 1/10 w , 1% , 0603 , smd 1 r 5 91 k ? res istor, 1/10 w , 1% , 0603 , smd 1 r 2 45 k ? res istor, 1/10 w , 1% , 0603 , smd 1 r3 10 k ? res istor, 1/10 w , 1% , 0603 , smd 1 r7 50 k ? res istor, 1/10 w , 1% , 0603 , smd www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 29 of 32 power dissipation and thermal consider ations power dissipation the efficiency of a dc - to - dc regulator is % 100 = in out p p efficiency (2 6 ) where : p in is the input power. p out is the output power. the p ower loss of a dc - to - dc regulator is p loss = p in ? p out there are four main sources of power loss in a dc - to - dc regulator : ? inductor losses ? power switch conduction losses ? switching losses ? transition losses inductor losses i nductor conduction losses are caused by the flow of current through the inductor dcr ( internal resistance ) . the inductor power loss (excluding core loss) is p l = i out 2 dcr l (2 7 ) power switch conduction losses p ower switch conductive losses are due to the output current, i out , flowing through the n - channel mos f et power switches that have internal resistan ce, r ds( on ) . the amount of power loss can be approximated as follows: p cond = [ r ds(on) C high s ide d + r ds(on) C l ow s ide (1 C d )] i out 2 (2 8 ) switching losses switching losses are associated with the current drawn by the driver to turn the power devices on and off at the swit ching frequency. each time a power device gate is turned on and off, the driver transfers a charg e ( ?q ) from t he input supply to the gate and then from the gate to ground. the amount of switching loss can by calculated as follows: p sw = q g_ total v in f sw ( 29) where: q g_ total is the total gate charge of both the high - side and low - side devices and is ap proximately 28 nc. f sw is the switching frequency . transition losses transition losses occur because the n - channel mosfet power switch cannot turn on or off instantaneously. during a switch node trans ition, the power switch provid es all of the inductor cur rent, and th e source - to - drain voltage o f the power switch is half the input, resulting in power loss. transition losses increase as the load current and input voltage increase, and these losses occur twice for each switching cycle. the transition losses ca n be calculated as follows: sw off on out in trans f t t i v p ) ( 2 + = ( 3 0 ) where t on and t off are the rise time and fall time of the switch node and are each approximately 10 ns for a 24 v input. thermal consideration s the power dissipated by the regulator increases the die junction temperature, t j , above the ambient temperature, t a , as follows: t j = t a + t r (3 1 ) where the temperature rise, t r , is proportional to the power dissipation , p d , in the package. the proportionality coefficient is defined as the thermal resistance f rom the junction temperature of the die to the ambient temperature as follows: t r = ja + p d (3 2 ) where ja is th e junction - to - ambient the rmal resistance and equals 40 c/w for t he jedec board ( see table 3 ). when de signing an application for a particular ambient tempera - ture range, calculate the expected ADP2441 power dissipation (p d ) due to the conducti on , swit ching, and transition losses using equation 2 8 , equation 29, and equation 3 0 , and then estimate the temperature rise using equation 3 1 and equation 3 2 . improved thermal performance can be achieved by implementing good board layout . for example, on the ADP2441 evaluatio n board ( ADP2441 - e va l z ), the measured ja is < 30 / w . thermal perfor - mance of the ADP2441 evaluation board is shown in the figure 64 and figure 65. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 30 of 32 evaluation board thermal performance 25 30 35 40 45 50 55 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 juntion temper a ture (c) ic power dissipi a tion (w) 10581-064 t a = 25c figure 64 . junction temperature vs. power dissipation based on ADP2441 - evalz 25 45 65 85 105 125 145 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 maximum ambient temper a ture (c) i c power dissipi a tion (w) 10581-065 figure 65 . maximum ambient temperature vs. power dissipation based on ADP2441 - evalz www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ADP2441 rev. 0 | page 31 of 32 circuit board layout recommendations good circuit board layout is essential for obt a in ing optimum performance. poor circuit board layout degrades the output voltage ripple ; the load, line, and feedba ck regulation ; and the emi and electromagnetic compatibility performance. for optimum layout, refer to the following guidelines: ? use separate analog and power ground planes. connect the ground reference of sensitive analog circuitry, such as the output voltage divide r comp onent and the compensation and frequency resistor , to analog ground. in addition, connect the ground references of power com ponents, such as input and output capacitors, to power ground. connect both ground planes to the exposed pad of the adp2 4 41. ? place one end of the input capacitor as close as possible to the v in pin , and connect the other end to the closest power ground pl ane. ? place a high frequency filter capacitor between the vin and pgnd pins , as close as possible to the p gnd pin . ? vcc is the internal regulator output. place a 1 f capacitor between the vcc and ag n d pins and another 1 f capacitor between the vcc and p gn d pin s . place the capacitor s as close as possible to the pin s. ? ensure that the high current loop traces are as short and wide as possible. make the high current path from c in through l, c out , and the power ground plane back to c in as short as possible. to accomplish this, ensure that the input and output capacitors share a common power ground plane. in addition, make the hig h current path from the pgnd pin through l and c out back to the power ground plane as short as possible. to do this, ensure that the p gnd pin is tied to the pgnd plane as close as possible to the input and output capacitors (see figure 66 ). ? connect the adp2 441 exposed pad to a large copper plane to maximize its po wer dissipation capability. ? pla ce the feedback resistor divider network as close as possible to the fb pin to prevent noise pickup. the length of the trace connecting the top of the feedback resistor divider to the output must be as short as possible while being kep t away from the high current traces and switch node to avoid noise pickup. place a n analog ground plane on either side of the fb trace to further reduce noise pickup. ? the placement and routing of the compensation components are critical f or optimum performance of ADP2441 . place t he compensation components as clos e as possible to the comp pin . u se 0402 size d compensation components to allow closer placement , which in turn reduces parasitic noise . surr ound the compensation componen ts with agnd to pr event noise pickup . ? the freq pin is sensitive to noise ; therefore, the frequency resistor should be located as close as possible to the freq pin and should be routed with minimal trace length . the small signal components should be grounde d to the analog ground path. fb comp en pgood freq ss pgnd vin sw bst agnd vcc ADP2441 v out v in c4 c3 c5 c6 c7 r2 r3 r5 r9 c10 v out notes 1. thick line indicates high current trace. 10581-066 figure 66 . high current trace c in c bst c out v in v out vcc fb comp freq pgnd agnd 10581-067 figure 67 . pcb top layer placement www.datasheet.net/ datasheet pdf - http://www..co.kr/
ADP2441 data sheet rev. 0 | page 32 of 32 outline dimensions 1.70 1.60 sq 1.5 0 0.50 0.40 0.30 072809 -b 1 0.50 bsc b o t t o m v i e w t o p v i e w 1 2 4 6 7 9 1 0 3 e x p o s e d p a d pin 1 indica t or 3.1 0 3.00 sq 2.9 0 sea ting plane 0.05 max 0.0 2 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 ind ica t or 0.30 0.2 3 0.18 compliant t o jedec standar ds mo-229-we ed-4. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.8 0 0.75 0.70 figure 68 . 12 - lead lead frame chip scale package [ lfcsp _wq] 3 mm 3 mm body, very very thin quad (cp - 12 - 6) dimensions shown in millimeters ordering guide model 1 output voltage temperature range package description package option ADP2441a cp z -r7 a djustable ?40c to + 125 c 12 - lead lead frame chip scale package [l fcsp_wq] cp -12-6 ADP2441 - evalz evaluation board preset to 5 v 1 z = rohs compliant part. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10581 - 0- 6/12(0) www.datasheet.net/ datasheet pdf - http://www..co.kr/

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